(1) Field of the Invention
The present invention relates to semiconductor processing for integrated circuits, and more particularly relates to a method for achieving accurate alignment of photomasks or reticles using improved global alignment marks (keys) on a substrate and a novel alignment algorithm.
(2) Description of the Prior Art
Semiconductor processing for forming integrated circuits on substrates (wafers) requires a series of processing steps. These processing steps include the deposition and patterning of material layers such as insulating layers, polysilicon layers, and metal layers. The layers are typically patterned using a photoresist layer that is patterned over the material layer by exposing the photoresist through a photomask or reticle. The photoresist is then developed to provide the pattern. Typically the photomask or reticle has alignment marks (keys) that are aligned to alignment marks formed on the substrate at a previous processing step. However, as the integrated circuit feature sizes continue to decrease for increased circuit density, it becomes more difficult to register or align one masking level to the previous level. This is particularly difficult at submicrometer feature sizes when the overlay alignment tolerances are reduced. The overlay metrology problem is further exacerbated when the material layer has an asymmetric profile over the alignment mark on the substrate. This asymmetry can result during deposition, for example, during spin coating, or during planarization processing, such as by chemical/mechanical polishing (CMP). One area where this is of importance is for the coarse or global alignment marks on the perimeter of the substrate. This asymmetry results in distortion of the detection signal used by the software algorithm when aligning the substrate on the substrate stage to the photomask/reticle in an align and-expose tool, such as in a step-and-repeat exposure system.
At submicrometer feature sizes, the planar surface is required because of the need for a shallow depth of focus (DOF) to avoid resist image distortions. This planar surface is also necessary to prevent residue, such as stringers or rails, from forming on steep topographies that, for example, can cause electrical shorts between adjacent metal lines when the next material layer is patterned using directional plasma etching.
To better appreciate the aligning problem associated with the asymmetric alignment marks, a schematic top view of a substrate 10 having a prior-art two-point global alignment mark metrology is shown in FIG. 1. FIG. 1 also shows the array of chip areas or die areas 11 in which the integrated circuits are fabricated, and the positions of the two alignment marks 12 at the periphery of the substrate.
FIG. 2 shows a greatly enlarged top-view of one of the two prior art alignment marks 12. These alignment marks are typically comprised of several arrays of grooves 13 that are aligned along the x- and y-axes of a rectangular coordinate system 2 aligned with reference to the substrate stage.
Referring now to FIG. 3, a schematic cross-sectional view is shown through a portion 3-3' of the alignment mark in FIG. 2 after the grooves 13 are formed. For example, the grooves can be formed by recessing the substrate 10 using a previous etching step. Also shown in FIG. 3 is a typical optical detection signal 14 that the optical system on the aligner/exposure tool would detect prior to depositing the material layer commonly used in fabricating integrated circuits. The peak amplitudes in the detection signal are generally aligned over the grooves, as depicted by the vertical lines Z, and result in accurately determining the position of the alignment marks relative to the referenced x-y coordinates for the substrate stage. Unfortunately, as shown in FIG. 4, when the required material layer 16 is deposited and is asymmetric, the edge detection signal 14' is shifted to Z' and an error in alignment of (Z-Z') results that can exceed the alignment tolerance for the given product.
Several methods for making improved alignment marks and methods for aligning the substrate using these alignment marks have been reported. For example, in U.S. Pat. No. 4,343,878 to Chiang, an alignment method is described for making a series of square alignment marks, such as Box-in-Box marks that also generate used key pair blot marks that provide self-instructing mask alignment information.
Caldwell, in U.S. Pat. No. 5,503,962, teaches a method of forming an alignment mark in a planar layer when etching via holes in an insulating layer. Since the insulating layer is totally planarized over the alignment marks, it is not possible to align a mask for the next metal layer, which is opaque. Therefore, Caldwell provides recesses in the insulating layer during etching of the via holes to provide an alignment mark. In U.S. Pat. No. 5,643,801 to Ishihara et al., a laser anneal method is described which also includes two alignment marks on the substrate and two cameras for aligning the substrate before annealing. Still another method is described by Turner et al. in U.S. Pat. No. 5,365,072 for aligning a microscope in which concentric square, circular, or triangular alignment marks are used to reposition a microscope, such as an Atomic Force Microscope (AFM).
However none of the above methods addresses the need to accurately align a photomask or reticle over an alignment mark having an asymmetric material layer on the surface. There is still a need in the semiconductor industry to provide an improved alignment mark metrology using improved alignment marks and an algorithm that minimizes or prevents edge detection errors when a material layer resulting in an asymmetric profile is used.